72 bit ddr3 interface with cyclone v SOC

We are implemeting the 72 bit ddr3 interface by using soft logic cores with cyclone v SOC having the part number 5CSXFC6D6F31I7.

This device does'nt support leveling feature to go with the standard Fly-by topology for the address,commond,Clock signals.

The above link suggesting balanced tree topology for the address,commond,Clock signals for 32 bit interaface.

Can anyone suggest me the To which topology i need to chose for the 72 bit ddr3 interafce.

DDR3 CLOCK FREQUENCY=303MHz

Regards

Ravi

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