7 segment display

FPGA: Cyclone II

software: Quartus II 9.0

I have a std_logic_vector number which I want to display on the 7 segment display.

meaning:

addr_reg: buffer std_logic_vector(log_2_of_num_of_states downto 1);

and the attribute was defined:

attribute altera_chip_pin_lc of addr_reg : signal is "@V13,@V14,@AE11,@AD11,@AC12,@AB12,@AF10"; (meaning all of HEX0)

but when I try to run it, the first hex representation doesn't show any number. I tried fixing it by converting the number to int first, but it still doesn't work and gives an alarming warning.

Thanks,