Honored ContributorHi,
I am working on stratix device. I have a design requirement to capture a pulse signal from a 50 Mhz domain to 20 Mhz. Please let me know, how can i capture these pulse without any pulse is missed. (Is there any specific Altera resource for synchronization) Regards, freak
Honored ContributorDo you need to count the pulses or capture their time?
You will have to do your capture logic in the 50MHz domain and transmit the information into the 20MHz domain. The only ready made component I know about to transmit information from one domain to the other is the dual clock fifo. If you don't need a fifo you'll have to do the synchronization yourself, using several cascaded registers to avoid metastability issues.Honored ContributorIf the pulse is less than 3 clocks wide in the 50MHz domain, it is impossible to sample it reliably in the 20MHz domain, unless you put it into a FIFO.
Honored ContributorHi Tricky,
I was just wondering, for a control signal transfer do we really need a FIFO interface. I guess this will be a common design requirement and how designers handle this without extending the pulse. Any more thoughts here ... Regards, freakHonored ContributorIt really depends how critical the system is. The basic setup is to double register a signal to prevent meta-stability. This will mean you need to hold the signal in the 50MHz clock domain for at least 3 clocks, or the 20MHz domain cant see it.
Ideally, you would have some form of handshaking - ie, you activate the signal in the 50MHz domain and wait until you get a response from the 20MHz before turning it off. This can slow the process down a lot, but it is much safer than simply passing it through a double register and hoping for a nice clean transition. A Fifo is really overkill for a single bit control signal. but for multiuple parralell bits, it garantees they all arrive in parrallel, rather than having some of them lag.Honored ContributorA synchronizer option that can be used with a single 50MHz pulse is called a toggle synchronizer.
In the 50MHz domain, the pulses toggle a signal. The toggle signal is the input to the 20MHz domain. In the 20MHz domain, there is a dual-DFF synchronizer, and a delay DFF, and the output of the synchronizer and delay are xored. This will generate a single pulse in the 20MHz domain. The pulses in the 50MHz domain must be far enough apart that the toggle exists for long enough that the 20MHz logic can see it. Cheers, DaveHonored ContributorHonored ContributorHere's a possible implementation for you.
Note that this particular implementation does not care about the clock in the originating domain of the pulse. The pulse itself is used as the clock to toggle a signal, and then the toggle signal is synchronized. Cheers, DaveHonored ContributorHere is the verilog equivalent, only that it goes through 2 synchronizers, and has independent asynchronous resets for each clock domain.
I can't remember where from the internet I pulled this from.module Flag_CrossDomain(
clkA,
reset_n_A,
FlagIn_clkA,
clkB,
reset_n_B,
FlagOut_clkB);
// clkA domain signals
input clkA, FlagIn_clkA;
input reset_n_A;
// clkB domain signals
input clkB;
output FlagOut_clkB;
input reset_n_B;
reg FlagToggle_clkA;
reg SyncA_clkB;
// this changes level when a flag is seen
always @(posedge clkA or negedge reset_n_A) begin
if (~reset_n_A) begin
FlagToggle_clkA <= 1'b0;
end
else begin
if(FlagIn_clkA) FlagToggle_clkA <= ~FlagToggle_clkA;
end
end
// which can then be synched to clkB
always @(posedge clkB or negedge reset_n_B) begin
if (~reset_n_B) begin
SyncA_clkB <= 3'h0;
end
else begin
SyncA_clkB <= {SyncA_clkB, FlagToggle_clkA};
end
end
// and recreate the flag from the level change (Takes 3 clocks. Went through 2 intermediate flip flops for extra stability)
assign FlagOut_clkB = (SyncA_clkB ^ SyncA_clkB);
endmodule
