Forum Discussion
4-8 Channel ADC for Altera DE2-115 using Simultaneous Sampling
We are building an Educational Embedded Computing System for a Road Profiler. I am incharge of taking care of the ADC interface to the DE2-115 board. Can anyone please suggest a suitable 16-bit standalone ADC which has on-chip flash memory, 4-8 Channels, Minimum Sampling Rate 1Mhz, Simultaneous Sampling Possible with all channels active and acquiring data, and that can be interfaced to the DE2-115 board using any protocol say I2C or using the HSMC interface?
There are cards available by Terasic, but they only have a 2 Channel 14-bit ADCs which can be interfaced to the HSMC connector. Also, we will be connecting a laser through the Ethernet Connector on the board and processing data. Is it possible to have Parallel Processing of the Data where all the data from the 4 Channels on the ADC and the data from the Laser can be simultaneously processed? We are completely new to the FPGA, including my professor. Hence we are all faced with tough challenges. Can somebody please help me out ASAP!!!13 Replies
- Altera_Forum
Honored Contributor
Stuart Sutherland's book are all very good on System Verilog, very readable. I suggest you also take a look at VHDL-2008. -James
- Altera_Forum
Honored Contributor
Yash,
Linear Tech does have an eval board for the LTC1407, the link for the board is shown below: http://www.linear.com/demo/dc1082a-a This would allow you to interface this board to something like the DE-NANO board from Terasic or similar. Also the circuitry is simply SPI; I would recommend using a pull up resistor on the CONV signal; otherwise SCLK and SDATA can be directly connected. Best, James - Altera_Forum
Honored Contributor
@ ames,
Can you let me know the circuitry involved for interfacing the LT-1407? I tried to find an evaluation board by LT, but couldnt find one. I guess you must've designed your own board and interfaced it to the Cyclone. I have a very basic and stupid doubt. Hope you can tend to it. Like you've read in my post earlier http://www.alteraforum.com/forum/showthread.php?t=36131 that I have data coming in from 4 analog channels, which I need to sample simultaneously, I forgot to mention the fact that I need the digital data out of it simultaneously too. Can you tell me how this would be possible using a SPI bus? Forgive my really basic questions, but my knowledge is still unclear. I am currently trying to understand the following datasheets of the ADCs: LT-1408 AD7606 ADS8556 I need to decide between them which one is best for my application. - Altera_Forum
Honored Contributor
@James:
Can you suggest a good reference material for learning and implementing System Verilog For Embedded and Verification applications? Something which progressively increases in the difficulty level and can make a apply my hardware knowledge well. Thanks a lot again for all the help until now. Will definitely ask for more! Yash - Altera_Forum
Honored Contributor
Very glad to meet everybody here,I am just a new member of this forum,I want to make more friends here,I hope you can like me.
- Altera_Forum
Honored Contributor
TI ADS8568 can achieve 400 kS/s over 8 parallel channels with a quad SPI interface. http://www.ti.com/product/ads8568
You need to interface an external PHY to implement an ethernet interface, I think, it's more convenient to use a DevKit with built-in PHY. - Altera_Forum
Honored Contributor
@FVM:
Sir, thanks for the valuable information. I dont require the HSMC interface because I will not be using such high speeds for my DAQ and sampling. A simple SPI interface will be sufficient for the application that we are planning to use in our research. That is the reason why I have been trying to look at the ADCs which I have mentioned above. Also, SPI interface drivers can be written/ the available ones I think so can be modified to suit my application. If you have any more valuable information to add, please do. Thanks again sir. PS: A quick question, is it possible to interface an Ethernet port to the DE-0 Nano board? If yes, how can it be done? Yash - Altera_Forum
Honored Contributor
I don't think that you'll find a HSMC daughter card according to your specifications. The said Terasic ADDA card, besides having only two channels also has transformer coupled in- and outputs and isn't suited for the intended frequency range without modifications.
TI offers a HSMC interface for their fast sampling ADC Evalboards. You can check if any of the available TI Evalboards is suited. Following your application requirements, I would primarly think of the family of parallel sampling SAR ADCs with parallel interface, e.g. offered by TI. But I'm not aware of ready-made HSMC daughter cards using these ADCs. - Altera_Forum
Honored Contributor
@Dave:
Thanks a lot. Yes, Terasic boards operate at very fast speeds. I am not trying to construct my own board for the time being. My professor too told me to look into existing boards and buy one out. I will test the signal that you are talking to me about and check its spectral response and see if I actually need a range of 16 bits. If not necessary, then I can definitely go for ADCs which are more accurate or I can go by your idea of oversampling the signal for a better SNR. Thank you Sir again for your valuable information. @James: I havent used either much, this is after 2 years that I am even getting back to Verilog programming. I appreciate all your help and advice. I will however be selecting the correct ADC and will soon begin work with it and keep in mind your advice about the the testing and design. Also, I might ask really lame and stupid questions or ask for help from time to time. Hope you dont mind helping me out. Thanks a ton Sir! Yash - Altera_Forum
Honored Contributor
In general, to interface the ADC to Nios, you would need to write a driver for the ADC and then make the data available on the Nios bus. I tend not to use Nios much, as I write at the microarchitecture and finite state machine level. But you will need to study the datasheet of whatever ADC you pick, and then create an appropriate interface. This mean adhering to the setup and hold times admonished in the data sheet, whether it be from TI, ADI, or Linear Tech, etc. For a serial ADC interface, the VHDL (or System Verilog) will typically have counters, shift registers, and a state machine.
What I recommend you to do is to pick an ADC, write the driver, and write the outputs of the ADC to a simple PWM DAC. Then use Signal Tap to scope the output of your ADC driver, using various analog inputs, to verify the driver is working correctly. This would be academic after performing the digital design with a proper testbench. Best, James