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14 years agoSee the coding guidelines for Q11.1
You need to use SystemVerilog for infered RAMs with byte enable access http://www.altera.com/literature/hb/qts/qts_qii51007.pdf Page 11-30See the coding guidelines for Q11.1
You need to use SystemVerilog for infered RAMs with byte enable access http://www.altera.com/literature/hb/qts/qts_qii51007.pdf Page 11-30