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BDegu's avatar
BDegu
Icon for New Contributor rankNew Contributor
5 years ago
Solved

3000A CLDL - occasionally powers on bad ?

I have a design that uses the EPM3128ATC100 CPLD. I have a couple of returned boards with the 3128 that have an odd problem that I need to understand:

When instrument is powered ON the CLPD will either be good and perform as designed, or it powers on in a bad state where the operation does not match the design. Once powered it is either good, or bad, so it seems like an something with how it is powering up. I'm a bit puzzled and worked on another issue for the past week but need to get back on this soon. Any thoughts would be appreciated.

Thanks, Bryan

  • cb01810's avatar
    cb01810
    5 years ago

    A quick look at Digikey indicates that many, if not all, of the EPM3128 family members are listed as "obsolete." This may not be a good part to be using in a new design, but check with your Intel rep to be sure.

    There are many possibilities for erratic CPLD behaviours, but most fall into these three categories:

    1. Not using a fully synchronous design structure (e.g. having gated clocks)
    2. Not debouncing / registering inputs, especially if they go to multiple places in a design or into state machines.
    3. Using the part outside of its limits (e.g., clock frequency, input setup times)
    4. Not including a global reset

    I hope this is helpful

3 Replies

  • cb01810's avatar
    cb01810
    Icon for New Contributor rankNew Contributor
    5 years ago

    A quick look at Digikey indicates that many, if not all, of the EPM3128 family members are listed as "obsolete." This may not be a good part to be using in a new design, but check with your Intel rep to be sure.

    There are many possibilities for erratic CPLD behaviours, but most fall into these three categories:

    1. Not using a fully synchronous design structure (e.g. having gated clocks)
    2. Not debouncing / registering inputs, especially if they go to multiple places in a design or into state machines.
    3. Using the part outside of its limits (e.g., clock frequency, input setup times)
    4. Not including a global reset

    I hope this is helpful

    • BDegu's avatar
      BDegu
      Icon for New Contributor rankNew Contributor
      4 years ago

      Thanks, This was very helpful. After reviewing and improving the reset for synchronous de-assertion it seems to be working correctly.

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    As suggested by other community user, we recommend you to follow the path. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you