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BDegu's avatar
BDegu
Icon for New Contributor rankNew Contributor
4 years ago
Solved

3000A CLDL - occasionally powers on bad ?

I have a design that uses the EPM3128ATC100 CPLD. I have a couple of returned boards with the 3128 that have an odd problem that I need to understand: When instrument is powered ON the CLPD will e...
  • cb01810's avatar
    cb01810
    4 years ago

    A quick look at Digikey indicates that many, if not all, of the EPM3128 family members are listed as "obsolete." This may not be a good part to be using in a new design, but check with your Intel rep to be sure.

    There are many possibilities for erratic CPLD behaviours, but most fall into these three categories:

    1. Not using a fully synchronous design structure (e.g. having gated clocks)
    2. Not debouncing / registering inputs, especially if they go to multiple places in a design or into state machines.
    3. Using the part outside of its limits (e.g., clock frequency, input setup times)
    4. Not including a global reset

    I hope this is helpful

cb01810's avatar
cb01810
Icon for New Contributor rankNew Contributor
4 years ago

A quick look at Digikey indicates that many, if not all, of the EPM3128 family members are listed as "obsolete." This may not be a good part to be using in a new design, but check with your Intel rep to be sure.

There are many possibilities for erratic CPLD behaviours, but most fall into these three categories:

  1. Not using a fully synchronous design structure (e.g. having gated clocks)
  2. Not debouncing / registering inputs, especially if they go to multiple places in a design or into state machines.
  3. Using the part outside of its limits (e.g., clock frequency, input setup times)
  4. Not including a global reset

I hope this is helpful

BDegu's avatar
BDegu
Icon for New Contributor rankNew Contributor
4 years ago

Thanks, This was very helpful. After reviewing and improving the reset for synchronous de-assertion it seems to be working correctly.