Forum Discussion
New Contributor3000A CLDL - occasionally powers on bad ?
A quick look at Digikey indicates that many, if not all, of the EPM3128 family members are listed as "obsolete." This may not be a good part to be using in a new design, but check with your Intel rep to be sure.
There are many possibilities for erratic CPLD behaviours, but most fall into these three categories:
- Not using a fully synchronous design structure (e.g. having gated clocks)
- Not debouncing / registering inputs, especially if they go to multiple places in a design or into state machines.
- Using the part outside of its limits (e.g., clock frequency, input setup times)
- Not including a global reset
I hope this is helpful
New ContributorA quick look at Digikey indicates that many, if not all, of the EPM3128 family members are listed as "obsolete." This may not be a good part to be using in a new design, but check with your Intel rep to be sure.
There are many possibilities for erratic CPLD behaviours, but most fall into these three categories:
- Not using a fully synchronous design structure (e.g. having gated clocks)
- Not debouncing / registering inputs, especially if they go to multiple places in a design or into state machines.
- Using the part outside of its limits (e.g., clock frequency, input setup times)
- Not including a global reset
I hope this is helpful
BDeguThanks, This was very helpful. After reviewing and improving the reset for synchronous de-assertion it seems to be working correctly.
