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Altera_Forum
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10 years ago

3.3V clock input on ddr3 i/o bank

Hi I have a board with a cyclone v (5CEFA2F23C8) and a ddr3 ram. On the same I/O-bank 7A as the ddr3 I have a clock input, as needed for running the ddr3-pll. My problem is, the pll does not lo...
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Altera_Forum
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10 years ago

Quartus won't let you do this. So, I suspect you've not specified the I/O standard of your clock input signal. Quartus will moan with a message such as:

--- Quote Start ---

Pin uses I/O standard 3.3-V LVCMOS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 1.5V.

--- Quote End ---

You'll need to change your clock signal to a 1.8V I/O standard or lower to drive into a 1.5V powered bank. This is detailed in the I/O Standard Specifications section, page 17, of the cyclone v device datasheet (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf).

Cheers,

Alex