Honored Contributor
Honored ContributorSOPC Builder: click on options for the ddr2 SDRAM High Performance Controller and then click on the tab Controller Settings.
OK: It works that way: Add the DDR2 SDRAM High Performance Controller. Do your settings at the Memory tab as well as at the PHY Settings Tab. Then click on the Controller Settings Tab and select "Enable error detection and correction logic". The click on ok(So u use only 30 Bits for 1 Gig of Ram). Then add a Avalon_MM Clock Crossing Bridge 2 times. Connect 1 to the S1-Port of the DDR2 Controller and the other to the ecc_slave port. The Addresses of the DDR2 Ram should start both at address 0x0(Otherwise you need more memory at the Clock Crossing Bridgets WITHOUT ANY advanteges! I hope I wrote it clearly. At least my SOPC builder generates vhdl-code and i only need 0x4000400 memory addresses instead of 0x8000000.
