16-bit 4 inputs interfacing with 16-bit 1 input of DCFIFO

first, does the clk input in the packetbitconverter block synchronizes the Q1...Q4 outputs ? (does the Q1...Q4 outputs changes on each edge of clk ?)if yes, then fulldataclk could be connected to clk

fifoclk is the clock connected to the wrclk of the fifo, choose for its frequency, any value that's at least 4 times bigger than fulldataclk (so as to be able to stock all the four values Q1..Q4 in the fifo, before they change)