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Hi,

Please follow the ATX PLL-to-fPLL Spacing Guidelines. Refer the link below.

https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transmit-plls-spacing-guideline-when.html

Thank you

Kshitij Goel

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you

Kshitij Goel