New ContributorIs there any timing files for MAX 10 - 10M04SCU324I7G FPGA? I'm trying to make a timing analysis using timing designer, but I can't find these timing file constrains.
Again, you have to create this for your design. It's not created for you because the tool has no way of knowing what your timing requirements are.
Super ContributorYou mean a .sdc file? You have to create that yourself for your design.
Super ContributorI would suggest you take a look into the wiki when you want to start writting your constrain:
https://community.intel.com/t5/FPGA-Wiki/Timequest-Static-Timing-Analysis/ta-p/735556
https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562
New ContributorThanks for your feedback. I already have all the timing constrains, but it will be best if we can have a timing file (.sdc or .td) instead of making it from scratch. I think it's under Cyclone 10 LP Devices.
Super ContributorAgain, you have to create this for your design. It's not created for you because the tool has no way of knowing what your timing requirements are.
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