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Honored Contributor10M02DCV36I7G - cheap, reliable clocking
I am new to MAX10s and pretty new to FPGAs in general, and will be using 10M02DCV36I7G as a peak detector. The inputs come from two single-ended comparator outputs.
I plan to use a number of phase-shifted clocks to minimize the timing uncertainty for when the peak was detected. For example four separate 400 MHz clocks each shifted a quarter period in relation to each other would give an uncertainty of 625 ps. The design needs to be low cost, low power and reliable, and I'm wondering if there is a downside to using a 5 MHz external crystal/oscillator with the 10M02 V36's internal PLL to generate four or five 400 MHz clocks. Anyone have some insights on this?11 Replies
Altera_ForumA 25MHz or 50MHz would probably be a better choice than 5MHz; as these frequencies are very common and the devices are readily available.
Multiplication factor would be 10X smaller at 50MHz vs 5MHz, s depending on the characteristics of your 5MHz device you might get better jitter performance at 50MHz. 5MHz is the absolute minimum input frequency to the PLL on a MAX10, so you would be right at the limit of the device capability.
