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Altera_Forum's avatar
Altera_Forum
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13 years ago

100 pF filter capacitor on TMS programming pin

Hello everybody,

Alter reccommends the use of a 10k pullup resistor to VDD on the TMS

JTAG pin to keep the input at VDD when in ioperational mode.

We are also considering a 100pF capacitor to GND to prevent spikes on our board (high power and high voltage design) from having influence on this pin, has anyone else done this as well ? The JTAG clock on the Altera USB blaster runs at 6 MHz, and from what I can see from the JTAG timing diagrams the TMS pin switches in every clock cycle, I would say a 100 pF cap should not prevent the ability of the USB blaster to program the CPLD ?

Thanks in advance for your answers,

Eric

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I don't think it would be a problem. That said once you have the footprint on the PCB it is easy to experiment with different values and see what works.

    If you have enough space on the board I'd recommend to use a LVTTL buffer between the FPGA and the JTAG header for protection. Put it close to the FGPA. We are using 74LVC541ABQ on our boards, they work very well and aren't that big (5x3mm in the QFN20 package)
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Why 100pF for TMS and not for TDI? How about TCK, the only edge sensitive JTAG signal?

    I would primarly suggest overvoltage protection for all JTAG pins, e.g. using high speed ESD diodes. In some situation, a small parallel capacitance for TCK seems to be necessary for reliable operation.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Ok to extend my question, the TMS pin, is this an open collector or TTL input ? This would have significant impact on the external circuitry we add to the pin.

    What about the other 3 JTAG programming pins ?

    Thanks in advance !

    Cheers,

    Eric
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If you keep TMS high then the JTAG state machine will stay in the TEST-LOGIC-RESET state even if there is noise on the other pins.

    Keeping noise off TCK is probably a good idea too - you can pull that up or down but pull-down is more common in the designs I've seen.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The pull-up resistor is necessary but if you add a capacitor too, it’ll help you reduce the spikes but will not give you the ideal result. I tried it on my Virtex-II board, it did reduce the spikes but it didn’t give me a very reliable 100% result.

    pcb assembly turnkey (http://www.7pcb.ca)