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Altera_Forum
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13 years ago

100 pF filter capacitor on TMS programming pin

Hello everybody, Alter reccommends the use of a 10k pullup resistor to VDD on the TMS JTAG pin to keep the input at VDD when in ioperational mode. We are also considering a 100pF capaci...
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Altera_Forum
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13 years ago

I don't think it would be a problem. That said once you have the footprint on the PCB it is easy to experiment with different values and see what works.

If you have enough space on the board I'd recommend to use a LVTTL buffer between the FPGA and the JTAG header for protection. Put it close to the FGPA. We are using 74LVC541ABQ on our boards, they work very well and aren't that big (5x3mm in the QFN20 package)