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Altera_Forum
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14 years ago

100 pF filter capacitor on TMS programming pin

Hello everybody, Alter reccommends the use of a 10k pullup resistor to VDD on the TMS JTAG pin to keep the input at VDD when in ioperational mode. We are also considering a 100pF capaci...
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Altera_Forum
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14 years ago

If you keep TMS high then the JTAG state machine will stay in the TEST-LOGIC-RESET state even if there is noise on the other pins.

Keeping noise off TCK is probably a good idea too - you can pull that up or down but pull-down is more common in the designs I've seen.