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Altera_Forum's avatar
Altera_Forum
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13 years ago

.rwdata and .bss do not work with custom memory controller

Hi,

I have designed a custom SRAM memory controller connected to a NIOS II processor that - as far as I can see - works. Running a test program from on-chip memory, reading/writing happens without any errors. It was only once I started assigning linker sections to the SRAM that I noticed something wasn't quite right (mainly, the JTAG UART was not working).

I am now in a situation where I have successfully executed a complex program where .entry, .exceptions, .heap, .rodata, .stack and .text are assigned to the SRAM and .rwdata and .bss are assigned to on-chip memory. If I dare assign .rwdata and .bss to the SRAM it stops working again and I am at a loss as to why this is happening.

Hoping that SignalTap would give me the answer, I wrote a short program that did read/write operations on static variables and again, everything worked fine, both in the logic analyser and the NIOS II debugger.

Would anybody have any suggestions/ideas what it could be?

Many Thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi,

    If you are using Qsys, it needs strict dynamis adressing. So, you must drive the byte enable of the SRAM in your custom controller to allow 8 and 16 bits accesses sometimes needed by Qsys component software drivers (exemple : TSE), even if your memory is 32 bits wide.

    Do you allow Qsys to drive them ?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Would seem that you have something wrong with the processing of write cycles.

    Possibly your simple test program is only writing to the data cache?

    It might also be that although single cycles work, adjacent writes or burst writes don't.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    It works! Thank you both for your replies :)

    All along I have been assuming it is a problem with the read/write bursts. Turns out pantxoa was right and I accidentally disconnected the byte enable signals. Merci beaucoup pantxoa, you have saved me a lot of bother!!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Happy to see it helps you !

    In fact, I already spent a lot of time on a similar issue, by trying to implement 32 bits ECC on a onchip NIOS CPU RAM ;-)

    Bye
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The other byte-enable 'GOTCHA' happens when using the PCIe to Avalon bridge - a PCIe cycle writing to a 32bit item ends up generating 2 bus cycles, the second of which has no byte enables asserted!

    So even though you only expect 32bit accesses you still need to look at (at least one of) the byte enables.

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