Where do I find the real VHDL training?

Thank you for sharing your experience so openly. I completely understand your frustration—VHDL can seem overwhelmingly complex and even redundant, especially if you’re coming from a software or schematic design background. You are definitely not alone in feeling this way; many engineers struggle with the same challenges.

A key difference with VHDL and other HDLs is that they describe hardware, not just a sequence of instructions like in C or other software languages. This means you’re building circuits where processes and signals operate in parallel, which is often a big shift in thinking if you’re used to software programming.

Regarding your specific questions about instantiation:
Yes, VHDL does require you to both declare a component and then instantiate it, which can feel repetitive. The component declaration is essentially a copy of your module’s interface, which VHDL uses to check that everything connects correctly—matching port names, data types, and directions. The instantiation then lets you create as many copies of that component as you need, each with its own connections in your top-level design. While it feels redundant, this approach helps prevent mismatches and wiring errors, especially in larger designs.

If you’re using a more modern VHDL tool or VHDL-2008, you might be able to instantiate entities directly without a separate component declaration, which can reduce the amount of repeated code. Also, many tools now offer graphical interfaces to help you visually connect modules, similar to schematic entry.

It’s great to hear you’ve had success with schematic designs—many people find that approach more intuitive. If you want to transition to VHDL, I recommend starting with very simple modules (like a counter or LED blinker), simulating your code, and building up from there.

If you’d like, please share a code example or a specific issue you’re facing with instantiation or any other VHDL feature. I’d be happy to walk you through it step by step. Sometimes, a real-world example makes all the difference.

You’re definitely not alone in this, and with the right support, it does get easier!

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My guess is that you are thinking about using an HDL the same way you'd use a standard software programming language, like C.  You can't think like that when coding in an HDL.  Every process operates in parallel since multiple signals can be driven simultaneously to different destinations in hardware.  This is probably the trickiest thing to overcome when learning an HDL.

As for your specific questions, if you post some code, folks here should be able to help.

Instantiation: VHDL require both a component declaration and the instantiation itself.  The component declaration defines the component's I/O ports and their data types and this must be defined because there are rules for how ports can connect to the rest of the design based on the direction, bus width, and data type.  Yes, the component declaration basically repeats the entity declaration from the component's .vhd file.  This is kind of a useful redundancy to make sure everything matches and connects correctly.  Once you have the component declaration, think about the fact that you could instantiate a component multiple times.  That's why the instantiation itself is separate and must be given a unique instance name.  The instantiation also defines how the instantiated component connects to the rest of the design, which is done through the port map.

If you're stuck on something, you should post code here.  Lots of folks can help.

Hello, 

You can get Altera training from here: https://www.altera.com/design/fpga-training/overview

regards,

Farabi