Looking for guidance on CXL IP access (university research, Agilex 7 I-series)
Our lab is currently conducting research on CXL-based systems, and we would like to use Altera’s CXL IP in our work. We already have an Agilex 7 I-series Development Kit, and we intend to integrate the CXL IP for non-commercial, academic research purposes only. However, when we contacted distributors such as Mouser and Digi-Key, we were informed that CXL IP is not available for sale in Korea now. Could you please let us know: 1. Whether CXL IP is available under a university license or academic program, 2. What the procedure is for a university in Korea to obtain or purchase the CXL IP (including any required forms, NDAs, or eligibility criteria), If there is a specific sales representative or regional contact we should speak with, we would appreciate it if you could connect us or share their contact information. Thank you very much for your time and support. I look forward to your guidance.Process for RMA - Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile)
Hello there, I have an Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) (https://www.altera.com/products/devkit/a1jui0000049utomam/agilex-7-fpga-i-series-transceiver-development-kit-6x-f-tile) that has recently stopped functioning correctly. In particular, the JTAG chain does recognize the existence of the Agilex FPGA. Quartus's JTAG debugger throws an error: Error: TDI connection to the first detected device 10M16S(A|C|L) might be shorted to GND Error: The TCK and TMS connections to the device before the first detected device 10M16S(A|C|L) might have a problem Info: Detected 1 device(s) Info: Device 1: 10M16S(A|C|L) When trying different settings on the JTAG chain selection mux, it is clear that the System MAX10 is detected and functioning correctly, but the Agilex FPGA cannot be detected. We have tried to reprogram the MAX10 with the factory default image, but there has been no change. We suspect a hardware issue with the JTAG chain. At this point, the Agilex FPGA is not accesible, rendering the board unusable for our purpose. Could ALTERA please support us on this? Is it possible to start the process for an RMA? Are there any options that we can consider? We greatly appreciate your assistance in this time of need Thank you
Can Instantiation components be repeated easier??
Hi all, When Instantiating multiple components, my U1,U2,U3 "adders" would be as follows: U1 : Adder Port map ( A => A, B => B, Sum => Sum); U2 : Adder Port map ( A => A, B => B, Sum => Sum); U3 : Adder Port map ( A => A, B => B, Sum => Sum); Is there a way (when using IDENTICAL components) to state something like the following code?: U1,U2,U3 : Adder Port map ( A => A, B => B, Sum => Sum);Where do I find the real VHDL training?
Hi All, After trying to master vhdl for 15+ years (on & off), i find vhdl to be incredibly over-complex and full of redundant coding techniques. I never truly know when (or why) i need to use a certain keyword instead of some other keyword, and choosing the options required between compiling/simulating/synthesising just loses me every time. I've watched over 200 vhdl beginner courses on youtube, i've paid $500 for approx 10+ udemy courses (which aren't much better than youtube videos. I own 50+ vhdl (at a cost of $2000), but i still don't understand what's being explained in the books. There are so many assumptions that i'm already a vhdl master, so i have no hope of moving forward with books. HOW do so many people know & use vhdl everyday like eating breakfast, i am LOST when i think about this secret 1% club. Are there any real courses spoken to ENGLISH people that i can understand? Feel free to share me your links... I'm yet to find some real training from beginners lever to intermediate that doesn't leave any vital information out. I still don't know how to truly instantiate my .vhd files, it seems to be redundantly repeating everything that i've already declared in my architectures. Why can't the instantiate code simply just refer to architecture names, or link to the external .vhd files???? In the past 15 years, ALL my quartus designs are strictly at a schematic level, where i can see what i'm connecting and follow the signal-flow easily and EVERY one of my projects simply work on day1. Is it ever likely that one day there will be a revised VHDL2? that eliminates all the entity/architecture/instantation redundancies? I feel that declaring ports/architecure/instantation should only be declared ONCE in anyones code. Maybe vhdl will fix all those silly anomolies...ONE DAY.Accessing Fabric PIO from the VxWorks on Arria10.
Hi, I am trying to Access the PIO IP instantiated on the FPGA fabric side from the VxWorks Application to toggle LED on the board. I did not find any example design/reference to understand how it works. Could you please help me understand how it works and how we target PIO memory address from the application. Also, where do we find the drivers of the FPGA IP cores? If i am not wrong it is at path: installation_folder>20.3>ip>altera>sopc_builder_ip>altera_avalon_pio. But when I do it this way I found below error messages. Kindly help me understand if i am missing something here. Thanks, Sukesh.Pednekar
Required lifecycle status for the MPN.
Hi Team, We are working in HCL Tech Chennai, India and supporting to Xerox corporation which is located in Webster NY US. As we belong to Component Engineer team taking care of lifecycle management. Please provide the lifecycle status of the below MPN's has we couldn't able to find in vendor site. If status gone Obsolete/NRND, please provide the respective document if available. MPN: PT31244 SL7GM Thanks, Ajithkumar
