Where do I find the real VHDL training?

My guess is that you are thinking about using an HDL the same way you'd use a standard software programming language, like C.  You can't think like that when coding in an HDL.  Every process operates in parallel since multiple signals can be driven simultaneously to different destinations in hardware.  This is probably the trickiest thing to overcome when learning an HDL.

As for your specific questions, if you post some code, folks here should be able to help.

Instantiation: VHDL require both a component declaration and the instantiation itself.  The component declaration defines the component's I/O ports and their data types and this must be defined because there are rules for how ports can connect to the rest of the design based on the direction, bus width, and data type.  Yes, the component declaration basically repeats the entity declaration from the component's .vhd file.  This is kind of a useful redundancy to make sure everything matches and connects correctly.  Once you have the component declaration, think about the fact that you could instantiate a component multiple times.  That's why the instantiation itself is separate and must be given a unique instance name.  The instantiation also defines how the instantiated component connects to the rest of the design, which is done through the port map.

If you're stuck on something, you should post code here.  Lots of folks can help.