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SYiwe's avatar
SYiwe
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

What's the reason of “Write per-bit deskew fail” during DDR4 calibration

Hi everyone,

Arria10 SoC DDR4 Interface calibration failed at the stage "write per-bit deskew", is there any Intel employee or FPGA customer knows the reason?

PCB design problem?

Power supply problem?

Time parameter problem?

Pin assignment problem?

FPGA IO termination problem?

Or anything else?

I'll be appreciated if anyone can help me loacte the problem so I can update software or hardware.

Thanks, regards.

4 Replies

  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hi SYiwe,

    There are a lot of reasons that can cause DDR4 calibration failure. For example as below:

    • Board design issue – FPGA power or RZQ termination issue
    • Quartus design timing closure issue – Is DDR4 design operating within spec ? Does Timequest DDR4 report show clean timing closure with positive margin ? Need to check this.
    • DDR4 IP setting issue – Make sure you verified all the setting in DDR4 IP is correct.
    1. I have attached excel file which a typical DDR4 calibration failure debug checklist where you can find detail debugging guildeline. This is for Arria 10 device but it is still useful for other device as well.
    2. Also you may go through and check this calibration checklist to see on the potential root cause that may impact the calibration. https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/devices/cfg-index/calibration-checklist.html

    I hope this helps.😊

    Regards,

    NAli1

  • 阳石000's avatar
    阳石000
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi SYiwe,

    Have you solved your problem about JTAG interface

    How did you solve it？

    I have the same problem as you.

    I'll be appreciated if you can tell me the answer.

    Thanks, regards.

    • SYiwe's avatar
      SYiwe
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      If your JTAG circuit is correct, probably beacuse your download cable doesn't support Arria10. I suggest you to change to a newer download cable, and it's better to be produced by Altera.

      Regards.

      • 阳石000's avatar
        阳石000
        Icon for New Contributor rankNew Contributor
        6 years ago

        The problem has been solved.I changed a USB BLASTER II. THANKS!

        I have a new problem.

        When I download jjc file to EPCQL1024 through JTAG interface, an error occurs "Error (209014): CONF_DONE failed to go high in device".

        Observe DCLK with an oscilloscope and find that there is no clock and nCSO is not pulled down.(EPCQL1024 replaced by MT25QU01G)

        Have you ever had such a problem？

        Thanks, regards.