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Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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What is the maximum Avalon memory-mapped interface data width supported for MAX 10 device?

Hi,

I want to use MAX 10 Fpga with NIOS II. I referred the below mentioned document. In this, it is mentioned that MAX 10 can support x16 interface ( in table 2.2 for various packages), but the maximum DQ groups is given only for X8 interface ( table 2.1).

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_emi.pdf

My query is as below:

1) How to calculate the avalon memory mapped data width for any device based on DQ group size?

2) Does Max 10 support x 16 interface?

3) If yes, what is the maximum of DQ groups in MAX 10?

Regards

Sbilg

  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    5 years ago

    Dear Susmita,

    Firstly, no problem for contacting us, It's what I'm here for. Even, me myself is also still learning. Learning process never ends I can say. So, don't be sorry 😊

    Interface width : The total number of DQ pins of the memory device.

    DQ/DQS group size: The number of DQ bits per DQS group.

    Let's say for example your total interface width (DQ width) is 16 bits.

    • The maximum supported DQ group size in Max 10 is 8bits.
    • So, there will be 2 group of data (DQS) which is 8 bits + 8bits =16 bits.

    To summarize based on above example:

    1. Total interface width = 16 bits
    2. DQ/DQS group size = 8 bits per DQS group
    3. Number of DQS group = 2

    Hope this helps.

    Thanks

    Regards,

    Aida

4 Replies

  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Dear Susmita,

    Firstly, no problem for contacting us, It's what I'm here for. Even, me myself is also still learning. Learning process never ends I can say. So, don't be sorry 😊

    Interface width : The total number of DQ pins of the memory device.

    DQ/DQS group size: The number of DQ bits per DQS group.

    Let's say for example your total interface width (DQ width) is 16 bits.

    • The maximum supported DQ group size in Max 10 is 8bits.
    • So, there will be 2 group of data (DQS) which is 8 bits + 8bits =16 bits.

    To summarize based on above example:

    1. Total interface width = 16 bits
    2. DQ/DQS group size = 8 bits per DQS group
    3. Number of DQS group = 2

    Hope this helps.

    Thanks

    Regards,

    Aida

    • Sushmita's avatar
      Sushmita
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi Aida,

      Thank you for the clarification.

      Regards

      Susmita

  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi Susmita,

    It’s me Aida. Hope you still remember me. Glad to serve you again. 😊

    Kindly refer to my reply below.

    1. How to calculate the avalon memory mapped data width for any device based on DQ group size?

    [Aida]: MAX 10 supports only Half rate, which results in a width of 4× the memory data width.

    2. Does Max 10 support x 16 interface?

    [Aida]: Yes, but not for all Max 10 devices and packages support x16 interface. Refer to Max 10 EMIF handbook under section Table 2-2: Supported Maximum External Memory Interface Width in MAX 10 Device Packages for MAX 10 device packages support that support x16 interface.--> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_emi.pdf

    3. If yes, what is the maximum of DQ groups in MAX 10?

    [Aida]: The maximum DQ group is x8 data.

    Hope this helps. Let me know if there are any concern/questions.

    Thanks

    Regards,

    Aida

  • Sushmita's avatar
    Sushmita
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi Aida,

    Thanks for replying again!

    I am a newbie to this field, sorry if my question is too basic. Your reply to my 1st and 2nd question helped me.

    With the third reply another question arises!

    What is the difference between Interface width and DQ size? How are they related?