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Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
6 years ago
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What is the maximum Avalon memory-mapped interface data width supported for MAX 10 device?

Hi, I want to use MAX 10 Fpga with NIOS II. I referred the below mentioned document. In this, it is mentioned that MAX 10 can support x16 interface ( in table 2.2 for various packages), but the maxi...
  • NurAida_A_Intel's avatar
    NurAida_A_Intel
    6 years ago

    Dear Susmita,

    Firstly, no problem for contacting us, It's what I'm here for. Even, me myself is also still learning. Learning process never ends I can say. So, don't be sorry 😊

    Interface width : The total number of DQ pins of the memory device.

    DQ/DQS group size: The number of DQ bits per DQS group.

    Let's say for example your total interface width (DQ width) is 16 bits.

    • The maximum supported DQ group size in Max 10 is 8bits.
    • So, there will be 2 group of data (DQS) which is 8 bits + 8bits =16 bits.

    To summarize based on above example:

    1. Total interface width = 16 bits
    2. DQ/DQS group size = 8 bits per DQS group
    3. Number of DQS group = 2

    Hope this helps.

    Thanks

    Regards,

    Aida

Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi Aida,

Thanks for replying again!

I am a newbie to this field, sorry if my question is too basic. Your reply to my 1st and 2nd question helped me.

With the third reply another question arises!

What is the difference between Interface width and DQ size? How are they related?