Sushmita
Occasional Contributor
5 years agoWhat is the maximum Avalon memory-mapped interface data width supported for MAX 10 device?
Hi, I want to use MAX 10 Fpga with NIOS II. I referred the below mentioned document. In this, it is mentioned that MAX 10 can support x16 interface ( in table 2.2 for various packages), but the maxi...
- 5 years ago
Dear Susmita,
Firstly, no problem for contacting us, It's what I'm here for. Even, me myself is also still learning. Learning process never ends I can say. So, don't be sorry 😊
Interface width : The total number of DQ pins of the memory device.
DQ/DQS group size: The number of DQ bits per DQS group.
Let's say for example your total interface width (DQ width) is 16 bits.
- The maximum supported DQ group size in Max 10 is 8bits.
- So, there will be 2 group of data (DQS) which is 8 bits + 8bits =16 bits.
To summarize based on above example:
- Total interface width = 16 bits
- DQ/DQS group size = 8 bits per DQS group
- Number of DQS group = 2
Hope this helps.
Thanks
Regards,
Aida