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Dexter22
New Contributor
New ContributorVerifying R-Tile PIPE Direct x8 lane-to-pin mapping on Agilex 7 I-Series Dev Kit
Hi all, I am bringing up a custom PCIe Gen5 controller on the Intel Agilex 7 I-Series Development Kit using the R-Tile Hard IP in PIPE Direct mode (1×16 bundle, only Octet 0 / lanes 0–7 active for n...
Wincent_Altera
Regular Contributor
Regular ContributorHi Dexter22 ,
For the Pin-out Guide , you may refer to
Agilex 7 Device Family Pin Connection Guidelines
Refclk connection for Octet 0 , you may check under section 2.2.1. Clocking
https://docs.altera.com/r/docs/683501/25.1.1/r-tile-avalon-streaming-ip-for-pci-express-user-guide/clocking?tocId=gEL4qX1L4Lucx8mOu~Rukg
let me know if there is anything unclear.
Regards,
Wincent_Altera
