Two Master RAM Access

Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII

Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connects with the DDR-RAM, and the NIOS II Processor also connects to the DDR-RAM

Templates i use : http://www.altera.com/support/examples/nios2/exm-avalon-mm.html?gsa_pos=2&wt.oss_r=1&wt.oss=avalon%20master%20template

now if i start the sof file the Signaltap shows my set options, and they seem to be ok. but when i start on NIOS IDE to programm anything it always tells:

Pausing target processor: OK

Initializing CPU cache (if present)

OK

Downloading 02000000 ( 0%)

Downloaded 43KB in 0.7s (61.4KB/s)

Verifying 02000000 ( 0%)

Verified OK

Leaving target processor paused

i only read with

a = IORD_32DIRECT(ALTMEMDDR_0_BASE,0);

printf("%d",a);

ALTMEMDDR_0_BASE is the Base Adress of the DDR RAM in the system.h

can anyone tell me what i have to do to access the DDR RAM with the NIOS II CPU as Master and via the Template Master that i controll via HDL???

Thx for ur help

René Gärtner