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Altera_Forum
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16 years ago

Two Master RAM Access

Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connect...
Altera_Forum's avatar
Altera_Forum
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16 years ago

It isn't the same thing. SOPC builder will do the arbitration so that the CPU and the HDL will share access to the RAM. But you still need to tell your HDL where to put the data.