TSE MAC related fitter error on Stratix III DSP DevKit

Hi all,

I've got a Stratix III DSP DevKit and have serious problems with the fitting process of the NIOS II standard design from the DevKit CD with both Quartus 8.0 and Quartus 8.1.

The error is related to a PLL used by the TSE MAC in the RMII configuration. This PLL is

connected to the RX Clock output of the Marvell PHY on the board.

The fitter error is:

Error: Can't place Left/Right or Top/Bottom PLL "enet_rx_clk_pll:enet_rx_clk_pll|altpll:altpll_component|enet_rx_clk_pll_altpll:auto_generated|pll1" -- I/O pin enet_rx_clk (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device

The enet_rx_clk is assigned to Pin AK_28 which isn't a dedicated CLK Pin of the FPGA.

I think that only dedicated CLK Pins on the FPGA can be connected to clock input ports of PLLs, so the fitter reports an error.

I proceeded as follows:

1.

I copied the folder from C:\altera\80\kits\stratixIII_3sl150_dsp\examples\stratixIII_3sl150_dev_examples\stratixIII_3sl150_dev_niosII_standard and opened

the project file.

2.

Then I ran Analysis&Elaboration, took a look at the PinPlanner and saw that all the top level enet_XXX ports and the oled_XXX ports were unconstrained.

3.

Ran the tse_mac_constraints.tcl file within Quartus and copied the Pin assignments from the stratixIII_3sl150_dev_enet.qsf file into the stratixIII_3sl150_dev_niosII_standard.qsf file (both files are in the project directory).

4.

Double checked Pin assignments in the PinPlanner with the DevKit reference manual.

5.

Started compilation and received the error upon.

I also tried to insert a CLKCTRL Megafunction between the input Port and the PLL, but the fitter still reported the same error.

Has someone experienced the same/similar problem yet and can help me out with this?

Regards,

Joki