Honored Contributor
Honored Contributorhi,
I'm facing a similar problem and for the moment all I have seen indicates that I should use an input pin for the ref clk instead of a PLL ouput, as you say... the problem is that in the development board I've got (with a stratix II gx) there is no 125MHz clocks, which should be the correct frequency for this ref clk, instead there is only one of 156MHz... there is an example design in altera's webpage that uses TSE MAC's with this board, and it seems to work using only this 156MHz clock, but I don't know how do they manage to feed an 125MHz clock to the TSE, or if simply they don't do it... anyone has had a similar problem? thanks a lot Fernando
