trace length of the PCIe

Dear Experts,

I am studying the PCIe of the Arria 10 SoC EVM board, the PCIe slot is defined for a root. I am going to use a crossover cable to connect it to a PC, and use it as a end point. I noticed that PCIe lanes is not required matching the length. How about the reference clock. I need make minor modification of the reference clock on the board(from driver to receiver）. so I can direct the reference clock from the PC to the FPGA on board. that will change the trace of the length. is there any requirement to the reference clock in length reference to the lanes. what is the timing requirement to the reference besides the 100Mhz frequency.

Thanks

David