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dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago
Solved

trace length of the PCIe

Dear Experts, I am studying the PCIe of the Arria 10 SoC EVM board, the PCIe slot is defined for a root. I am going to use a crossover cable to connect it to a PC, and use it as a end point. I n...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    4 years ago

    Hi David,


    The Intel Arria 10 Hard IP for PCI Express supports for Separate Reference Clock No Spread Spectrum (SRNS) architecture. The Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture is not supported. For SRNS, you have to make sure that the worst case is 600 ppm.


    Thanks

    Best regards,

    KhaiY


KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi David,


The Intel Arria 10 Hard IP for PCI Express supports for Separate Reference Clock No Spread Spectrum (SRNS) architecture. The Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture is not supported. For SRNS, you have to make sure that the worst case is 600 ppm.


Thanks

Best regards,

KhaiY