Forum Discussion

gongmh's avatar
gongmh
Icon for New Contributor rankNew Contributor
2 years ago

The question about arria10-netlength

hello,

I downloaded this table(10AS032EF29_netlength.xlsx) from the official website, but there are two columns in it: Total Length (mm) and Total Delay (ps). Which data should I take as the criterion? What value should I set in the PIN DELAY of the PCB?

Board Debug

11 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    You may use Total delay(ps) as your pin delay setting.


    regards,

    Farabi


    • gongmh's avatar
      gongmh
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hello, Farabi

      Thank you very much for your answer.

      I still have questions:

      why is the the ratio of "total length(mm) "and "Total delay(ps) " different？It's supposed to be a fixed ratio。

      or what is the difference of the "total length(mm) "and "Total delay(ps) "?

      Best Wishes.

      • gongmh's avatar
        gongmh
        Icon for New Contributor rankNew Contributor
        2 years ago

        Hello,

        Can anyone answer that? thanks a lot.

        best wishes.

    • gongmh's avatar
      gongmh
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hello，

      first, I think the ratio of length to time represents the rate, it's a constant value.

      second,The purpose of equilength is isochronous. The length should equal the length of the delay.（1mm=39.72mil ， in FR4 PCB, 1ps≈6mil ）

      If they're not equal, it's a proportional relationship. I don't know if I understand this right?

      Regards,

      gongmh

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Okay, thank you for feedback.

    I am consulting the internal team to get the confirmation on this matter. I will come back to you with the answer as soon as possible.

    Thank you for your understanding.


    Regards,

    Aqid


  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    I got some input from the internal team on this question.


    This design has been routed in strip line and microstrip line routing. These two have a difference speed between them. The speed in the microstrip line is faster compared to the strip line. Thats why the ratio is not fix.


    Regards,

    Aqid


    • gongmh's avatar
      gongmh
      Icon for New Contributor rankNew Contributor
      2 years ago

      hello ,

      Do you mean that there are microstrip lines and strip lines inside the FPGA? So the two values are different?

      My understanding is that the delay should be the same in FPGA inside, Because the routing is already established.

      best wishes,

      gongmh

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    • gongmh's avatar
      gongmh
      Icon for New Contributor rankNew Contributor
      2 years ago

      hello,

      thanks for you help.Is there anyone who can answer my question?