Stratix 10 MX Development Kit - Low Latency 100G IP Core Design Example Problems
Hi,
I am using the Stratix 10 MX (8 Gb) Development Board (Device: 1SM21BHU2F53E2VG) to test out the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example on Quartus v19.1.
I have reached step 1.8 in the design example user guide successfully, but I am getting a very weird results to no results. I have no idea why the IP core is not working as intended. I have attached the .qsf file, the System Console output, and the Ethernet link screenshots.
IP Core User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_ll_100gbe.pdf
Design Example User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-ll-100gbe.pdf
Thank you.
Hi,
By referring to the qsf file, it looks like you did not do the pin assignment correctly, you are testing the QSFP /100G ethernet, but you assign the clock and TX/RX Pin to PCIe. Please refer to the user guide or the schematic below for more detail:
Regards -SK