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Larsgrantz's avatar
Larsgrantz
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Stratix 10 MX Development Kit - Low Latency 100G IP Core Design Example Problems

Hi, I am using the Stratix 10 MX (8 Gb) Development Board (Device: 1SM21BHU2F53E2VG) to test out the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example on Quartus v19.1. I have rea...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Lars,


This is glad to see the problem resolved. If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


Regards -SK