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Larsgrantz
New Contributor
New ContributorStratix 10 MX Development Kit - Low Latency 100G IP Core Design Example Problems
Hi,
I am using the Stratix 10 MX (8 Gb) Development Board (Device: 1SM21BHU2F53E2VG) to test out the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example on Quartus v19.1.
I have rea...
Hi,
By referring to the qsf file, it looks like you did not do the pin assignment correctly, you are testing the QSFP /100G ethernet, but you assign the clock and TX/RX Pin to PCIe. Please refer to the user guide or the schematic below for more detail:
Regards -SK
SengKok_L_Intel
Regular Contributor
Regular ContributorHi Lars,
This is glad to see the problem resolved. If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
Regards -SK
