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Larsgrantz
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5 years ago
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Stratix 10 MX Development Kit - Low Latency 100G IP Core Design Example Problems

Hi, I am using the Stratix 10 MX (8 Gb) Development Board (Device: 1SM21BHU2F53E2VG) to test out the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example on Quartus v19.1. I have rea...
Larsgrantz's avatar
Larsgrantz
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5 years ago

Hi Sengkok,

Thanks for pointing the incorrect pin assignment out!

Unfortunately, I am having the same poor results where nothing appears to be working. I have attached the updated qsf file.

Thanks,

Lars