Stratix 10 JTAG to Avalon Master Bridge Exception

I am attempting to use the JTAG to Avalon Memory Map Master Bridge IP core with a Stratix 10 Signal Integrity Kit but when I program the board with the System Console I get an exception saying that no SLD nodes will be created for the device; I have also tried programming the board with the standalone programmer and communicate with the core through the system console but in that instance there is no exception but no reads or writes will finish.

I first noticed this error with the 10G Ethernet MAC example design and have also created a project that only contains the JTAG core, a PIO, and clock and reset source that throws the same exception. When I remove the JTAG core from the example design it programs without issue but I am unable to test the rest of the functionality because the JTAG core is the only way I have to communicate with the chip.