Stratix 10 DDR4 timing model & package model

Hi Adzim,

Thanks for the link to the models.

After thinking about it more, I came up with this idea that since this is an FPGA device, one simulation model received from you could not be applied to all applications and FPGA programming. We (our FPGA developer team) should be generating it by the tool they used to develop this FPGA, so the model pins match the programmed FPGA pins. Do you agree and does the tool have this option?

There is also ODT issue in my simulation. The option to select/change ODT in the simulation tool is grayed out. This reinforces my idea of having to generate the IBIS model in the tool used to develop the FPGA after it is fully developed.

As for DDR4 timing model, there is a SDRAM DDR4 timing model and Controller DDR4 timing model. In this case the FPGA is the controller. However, some vendors direct the user to follow the JEDEC standard some provide their own version. If Altera/Intel does not supply such model, then I will use the JEDEC standard which is the default model in the simulation tool.

Thanks

Ali