Honored ContributorI am trying to read a bunch of data from SSRAM (IS61LPS25636A)) on Cyclone III, which is 256k*32 bit in size. However, from the board manual, there are 32 data bits, 21 address bit (should be 18 bits for 256k), Does anybody know this problem? what are the additional three pins?
Honored ContributorNo it is the opposite. ADSC is active low so you need to put 0 to load the address. Have a look at the diagrams in the datasheet.
Honored ContributorI followed you idea to make ADSC as 0, but still can not get data from different address as attached.
In addtion, which data sheet did you refer to? From attached, it seems the ADSC_N should be always zeros.Honored ContributorThe waveforms that you have now look correct. Are you sure that those signals are connected to the correct pins outside the FPGA? Is the flash disabled?
It may sound stupid but are you sure that the first addresses in the SRAM hold different values?Honored ContributorI checked the values in the first several addresses, they are different
Here I attached new signals. I put the values as FFFFFFFF, 05060708h,090A0B0Ch, 0D0E0F10h, 11121314h,....in the first addresses of the ssram memory. I still can not get the different values at the rising edge of clk_test. But it seems near to succeed. I also checked and attached the pin assignment. what's the flash disabled? I have no idea about this.Honored ContributorThe SSRAM and the flash share the address/data bus. You must be sure that the flash OE_n and CE_n pins are maintained at '1' so that the flash doesn't drive the data bus. It is only connected to the 16 low bits though, so it shouldnt' cause your problem anyway.
How did you write those values in the SSRAM? Was it using another design? In this design your data lines are inputs only. The clock for the SSRAM is connected to pin A2. Are you providing it? ssramclk_test is connected to D3. You could also try to put ssram_oe_n always at 0. It shouldn't be necessary but it could be worth a try.Honored ContributorThe SSRAM and the flash share the address/data bus. You must be sure that the flash OE_n and CE_n pins are maintained at '1' so that the flash doesn't drive the data bus. It is only connected to the 16 low bits though, so it shouldnt' cause your problem anyway.
I tried , but it did not work as attached How did you write those values in the SSRAM? Was it using another design? In this design your data lines are inputs only. I used the control pannel to write valules manually, which is a integrated software in quartus. The clock for the SSRAM is connected to pin A2. Are you providing it? ssramclk_test is connected to D3. I attached the schematics for this project, you can see that the pins here are only for output monitor. The signal source come from 50MHz source via pll. You could also try to put ssram_oe_n always at 0. It shouldn't be necessary but it could be worth a try. I tried, it does not work, as attched. Did you successful read data from ssram before? ThanksHonored ContributorYes I have a design that connects an avalon slave bus to a SSRAM, and can read and write.
When you wrote the values in the SSRAM, was it with a different configuration in the FPGA? Your design isn't able to write to the SSRAM. I didn't find the schematics in your attachments.Honored ContributorHere is the attachment. I used different configuration for write and read. I use control panel to write(one available sof file from altera) then use another sof file(mine) to read.
Honored ContributorYour document is difficult to read, the resolution is too low.
I didn't find any clock output to the ssram clock (pin A2). Where is it? I can have a look at your project this week-end. My email address can't receive 20M, but you can use a service such as http://demo.ovh.org/ and send me the link in a PM.Honored ContributorThe project can be found here. Thanks a lot, Daixiwen.
http://demo.ovh.org/en/93355c7dd00ae875a0232675a88cdde3/
