SSRAM (IS61LPS25636A)) on Cyclone III starter board

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There is no problem. A20 and A19 are marked as NC (not connected) in the schematic. A18 is also without function, as the ISSI datasheet clarifies. They are reserved for same package, higher capacity parts.

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FPGA manual

http://www.issi.com/pdf/61vps_lps25636a_51218a.pdf

and the manual for this board here

http://www.altera.com/literature/ug/ug_ciii_starter_kit.pdf (http://www.altera.com/literature/man...rter_board.pdf)

Hi, Do you mean A20 A21, A22 As shown above in the manual? I can not find information about "They are reserved for same package, higher capacity parts."

Did you successfully read data from it using verilog/VHDL? Thanks.

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Do you mean A20 A21, A22.

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Yes, the pin names are different between schematic and reference manual. The pins are functionless and don't need to be connected to your design.

I tried to use the following code to read a set of data from SSRAM, but found I can only get the very first data in address 18'b0; can not read others even I changes the address.

Can anybody help about this? Thanks.

`timescale 1ns / 1ps

module mem_read(

ssram_clk,

clk,

reset_n,

ssram_adsc_n,

ssram_bw_n,

ssram_bwe_n,

ssram_ce_n,

flash_ssram_a,

flash_ssram_d,

ssram_oe_n,

test_led

);

input ssram_clk;

input clk;

input reset_n;

output wire ssram_adsc_n;

output wire [3:0] ssram_bw_n;

output wire ssram_bwe_n;

output wire ssram_ce_n;

output wire [19:2] flash_ssram_a;

input [31: 0] flash_ssram_d;

output reg ssram_oe_n;

output wire [3:0] test_led;

assign ssram_adsc_n=1'b1;

assign ssram_bw_n=4'b1111;

assign ssram_bwe_n=1'b1;

assign ssram_ce_n=1'b0;

// assign flash_ssram_a=counter1;

// assign ssram_oe_n=1'b0;

reg [1:0] counter;

always@(posedge ssram_clk, posedge reset_n)

begin

if (reset_n)

counter <=2'b00;

else if (counter1==18'b111111111111111111)

counter <=2'b00;

else if (counter==2'b11)

counter <=2'b01;

else

counter <= counter + 2'b1;

end

//counter

reg [17:0] counter1;

always@(posedge clk, posedge reset_n)

begin

if (reset_n)

begin

counter1 <= 18'b111111111111111111;

end

else if (counter1==18'b111111111111111111)

counter1<=18'b000000000000000000;

else

begin

counter1<=counter1+18'b1;

end

end

assign test_led[0]=reset_n;

assign flash_ssram_a =counter1;

always @(negedge ssram_clk, posedge reset_n)

begin

if (reset_n)

begin

ssram_oe_n <=1'b1;

end

else if (counter1==18'b111111111111111111)

begin

ssram_oe_n <=1'b1;

end

else if (counter==2'b01||counter==2'b11)

begin

ssram_oe_n <= 1'b1;

end

else if (counter==2'b10)

begin

ssram_oe_n <= 1'b0;

end

else

;

end

endmodule

The name reset_n suggests that your reset signal is active low, but in your code you are resetting your system when it is 1... are you sure you aern't keeping yr design in permanent reset?

Are the clocks clk and ssram_clk related? You are crossing from one domain to the other without any protection and it could cause problems.

Yes, I took care of the reset_n, and used a inverter before reset_n on the button on FPGA.

clk and ssram_clk are related as they are the pll outs from single master clk(50MHz).

Thanks.

I can send you all the project source if you are interested. It's about 20 M.

My msn:feizhang@hotmail.com

Try to put everything on a rising edge of the clock, it will make it easier to see what is going on.

To perform a read you also need to put a 0 on either /ADSP or /ADSC to load the address into the memory.

Thanks, i have ADSC_n to 0 as above code, but it still can not work, I mean it can only get the first value at 0 address always.

Daixiwen: could I send you the whole project? If possible, please help me check.

Attached is the signals including control line

I don't have access to quartus during this week so it would be difficult for me to check your project.

On the screenshot that you show, ADSC_n is 1 so the address is never loaded by the SRAM.