Honored Contributor
Honored ContributorThe SSRAM and the flash share the address/data bus. You must be sure that the flash OE_n and CE_n pins are maintained at '1' so that the flash doesn't drive the data bus. It is only connected to the 16 low bits though, so it shouldnt' cause your problem anyway.
I tried , but it did not work as attached How did you write those values in the SSRAM? Was it using another design? In this design your data lines are inputs only. I used the control pannel to write valules manually, which is a integrated software in quartus. The clock for the SSRAM is connected to pin A2. Are you providing it? ssramclk_test is connected to D3. I attached the schematics for this project, you can see that the pins here are only for output monitor. The signal source come from 50MHz source via pll. You could also try to put ssram_oe_n always at 0. It shouldn't be necessary but it could be worth a try. I tried, it does not work, as attched. Did you successful read data from ssram before? Thanks
