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Altera_Forum
Honored Contributor
15 years agoThe SSRAM and the flash share the address/data bus. You must be sure that the flash OE_n and CE_n pins are maintained at '1' so that the flash doesn't drive the data bus. It is only connected to the 16 low bits though, so it shouldnt' cause your problem anyway.
How did you write those values in the SSRAM? Was it using another design? In this design your data lines are inputs only. The clock for the SSRAM is connected to pin A2. Are you providing it? ssramclk_test is connected to D3. You could also try to put ssram_oe_n always at 0. It shouldn't be necessary but it could be worth a try.