SRAM K1B3216B2E on Cyclone III Development Kit

From what I can read, you don't have any hold or wait states for write access.

You can try this one, that I used on the board a while ago. It is rather slow with some conservative timing figures, but it should work.

Hi Reto,

I had a look at the sopc schematic.

I believe your addressing is not right(assuming altera haven't change the tristate bridge addressing scheme from what I had used before).

You have grounded address bit(0) then you discard address bits(2:1). This means you are discarding 3 bits off avalon address. I will not ground any address bit and then discard bits(1:0).

I am not familiar with dev boards, so you must get other people's advice regarding other signals.

Kaz

TO Daixiwen: thank you for your example! Unfortunately, it doesn't work, when i run my nios II project (hello world) on it. nios ide can validate the sram, but the program doesn't run properly (my uart doesn't send any characters...)

did you set 'data' and 'address' as shared signals in tristate_bridge (sopc builder)?

TO kaz: i grounded address bit 0, because the sram-address-port addressSRAM(0) is connected with adressSFBus(1) and addressSRAM(20) is connected with adressSFBus(21). so i only discard addressSOPC(0:1). i hope it is clear now... difficult to explain for me without a picture.

Altera wrote me this:

When you create a SOPC component based on HDL file, you can’t use tri-state MM slave interface. sram K1B3216B2E can be used as popular sram. I have attached the component, you can use it. If you are using the standard example shipped with the kit, please check the pin assignments of fsd16~fsd31. There are several errors please correct them according the reference manual.

The option bits address is 0x3fe0000 instead of 0x380000. Page 1 start address is 0x380000. Please refer to the attached screen shot to program the flash.

reto's opinion and questions:

- to the pin assignment: does anybody know where i can found the correct pinout? i checkt it several times with schematic and reference guide, but didn't found any error.

- i can't set options address on 0x03fe0000, because its an cfi_64MB, not a cfi_512MB, so address range is smaller than 0x03fe0000. what's the correct options address?

thank you for any help, i'm loosing my patient bit by bit!

reto

The only signals I have shared are data and address. I only had one bit to remove from the address bus (see attached picture), but it may be different than your system because I don't use the flash at all.

If you used some of Altera's design example projects as a start, some data pins are not connected properly. See this message (http://www.alteraforum.com/forum/showthread.php?t=2609) and change your assignments accordingly, if required.

I think that you should start with a very simple SOPC system, with only what's necessary for a memory test (CPU, big on-chip memory, SRAM, JTAG UART, System ID). Then compile the memory test example, run it from the on-chip memory, and ask it to test the SRAM. Then you should be able to see if it fails completely or partially. If you still can't understand what's going on, use a SignalTap probe to check the SRAM signals.

Hi Daixiwen,

thank you for your picture. when i connect your sram component like this, nios II ide load the firmware correct (.text, .rodata, .rwdata) into the sram and verify it successfully.

but if i run the programm, it doesn't work (hello world to jtag-uart). did you set some timing constraints for output pins? e.g. 1ns clock to output delay (in assignment editor of quartus II)?

thank you very much for your help!

regards,

reto

I've put these constraints, but I'm not sure they are necessary, as it is an asynchronous interface and the setup and hold times on the SOPC component are larger than the actual requirements of the SRAM.

create_clock -name {clkin_50} -period 20 -waveform { 0 10 } 
set_input_delay -clock clkin_50 -max 15 }]
set_input_delay -clock clkin_50 -min 0 }]
set_output_delay -clock clkin_50 -max 15  fsa sram_ben sram_csn sram_advn sram_oen sram_wen sram_psn sram_clk}]
set_output_delay -clock clkin_50 -min -4  fsa sram_ben sram_csn sram_advn sram_oen sram_wen sram_psn sram_clk}]

Downloading the software in SRAM through the IDE doesn't fully test the memory. Have you tried to compile the "memory test" design example in on-chip RAM, and have it test the SRAM?

Does your "hello word" program work from on-chip memory?

Have you tried to compile the "memory test" design example in on-chip RAM, and have it test the SRAM?

--> yes, it's strange. the memory test passed every bit, byte and half-word access!

Does your "hello word" program work from on-chip memory?

--> yes, my hello world works from on-chip ram and sdram, but not from my sram...

next step will be: setting your timing constraints!

!!!!!!!!!!!!!!!!THANKS A LOT!!!!!!!!!!!!!!!!!!!!!

Regards,

Reto

Here the component which works with my board. It's quit slowly, but reliable :) .

!!! If anybody can speed it a little up, please let me know !!!

Thanks to you Daixiwen and kaz!!!

Reto

Unfortunately the SRAM is used in asynchronous mode, and can't be used a lot faster than this. I don't understand why your system doesn't work with my timings though, this is very strange...

If you want to speed up the interface, you would need to write a controller in VHDL or Verilog, to handle burst transfers. Unfortunately burst transfers can't be used with tristate bridges AFAIK, so this means you wouldn't be able to use the flash at the same time any more...

Hi,

Can you please let me know how fast is the SRAM component. What is the the performance?

Regards

Foram