Occasional ContributorSignalTap Logic Analyzer rapid compile failure
Hello,
I am using the Signal Tap II logic analyzer on Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Standard Edition. I have been tracing logic in the Cyclone V SOC for over a month. Since yesterday I am encountering a problem with rapid compile. A problem report message box pops up, see attached PNG file. I provide a copy of the report. The following errors are presented in the messages:
Error (281039): Finished parallel synthesis of 1 partition(s). 2 partitions did not finish parallel synthesis because there were errors
Error (281040): Partition "sld_hub:auto_hub" did not complete synthesis due to errors
I found descriptions for these messages in the Quartus Help app. It states that the errors occurred because of a prior error. I did not find any error previous to 281039. I searched through the various reports and found no error messages. I scanned through the queries relating to Signal Tap and did not find a relevant post.
If I disable Signal Tap the error does not occur. Here are a list of steps I have tried:
Cleaned the project and ran a full compile with Signal Tap disabled.
Reverted to a previously working STP file.
The current failure occurred after performing the above steps.
Please let me know if I need to provide more information.
Thank you
The screenshots indicate a Quartus crash, not errors with the compile like you state. Easiest thing to do is delete the db and incremental_db folders and recompile from scratch.
If you're saying that even after this, with the current .stp file that Quartus is still crashing when the .stp is enabled, it's possible that your .stp file is corrupt. Create a new one and match the settings you have.
