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Altera_Forum's avatar
Altera_Forum
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8 years ago

SDRAM Usage for the DE1-Soc Board

Hi guys,

I want to save data in the SDRAM and afterwards to read out the data from the SDRAM.

For my project, I used the Qsys and implemented the components afterwards in my VHDL code.

When I check the results in the signal analyzer, I only got a value for the writedata operation.

Could anybody help me? Does anybody know a good tutorial for the usage of the SDRAM?

Thanks,

Chris

This is an extract of the source code --> architecture :

process(CLK143)

begin

if rising_edge(CLK143) then

SDRAM_WE_N<='1';

SDRAM_WRITEDATA<="1111111111111111";

SDRAM_RE_N<='1';

RAMIN1<=SDRAM_READDATA(7 downto 0);

end if;

end process;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hello Christoph,

    SDRAM is a complex chip that requires special logic to operate.

    It needs an external refresh mechanism to keep it going, I think this aspect is not in your code.

    Best Regards,

    Johi.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    Hello Christoph,

    SDRAM is a complex chip that requires special logic to operate.

    It needs an external refresh mechanism to keep it going, I think this aspect is not in your code.

    Best Regards,

    Johi.

    --- Quote End ---

    Hi John,

    thank you for your information. I added you the latest code below.

    process(CLK143)

    begin

    if rising_edge(CLK143) then --write process

    --case BUFF_CTRL is

    --when st0=>------------write image to SDRAM

    --if (SDRAM_WAIT='0')then

    SDRAM_WE_N<='0';

    SDRAM_RE_N<='1';

    --SDRAM_WRITEDATA<="1010101010101010";

    DRAM_DQ(15) <= '0';

    DRAM_DQ(14) <= '0';

    DRAM_DQ(13 downto 0) <= ADC_DB(13 downto 0);

    SDRAM_WRITEDATA<=DRAM_DQ;

    SDRAM_ADDR<=std_logic_vector(unsigned(SDRAM_ADDR)+1);

    --end if;

    --when st1=>-----------write from SDRAM to BUFFER

    SDRAM_WE_N<='1';

    --RAMWE1<=SDRAM_RDVAL;

    --SDRAM_RDVAL<='1';

    RAMWE1<='1';

    SDRAM_RE_N<='0';

    SDRAM_WAIT<='0';

    SDRAM_ADDR<=std_logic_vector(unsigned(SDRAM_ADDR)+1);

    RAMIN1<=SDRAM_READDATA(15 downto 0);

    --end case;

    end if;

    end process;

    I am able to write the data but when I read it, I got the wrong value.

    Do I have to implement the whole FSM to use the SDRAM properly?

    Thanks,

    Chris
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi Christoph,

    i'm also trying to get a working memory interface on my DE1-soc board right now.

    --- Quote Start ---

    Hello Christoph,

    SDRAM is a complex chip that requires special logic to operate.

    It needs an external refresh mechanism to keep it going, I think this aspect is not in your code.

    Best Regards,

    Johi.

    --- Quote End ---

    what he's saying, you need a memory controller, thus can be integrated by using IP Cores, otherwise the Memorycontent wont be safed, because s"D"ram is dynamic, which means, bits are stored to capacitators which must be refreshed. (by a controller.)

    I consider right now using the onboard DDR3RAM, because its faster, but cant get any IP wordking till now on Quartus 17.1 ...