Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi Christoph,
i'm also trying to get a working memory interface on my DE1-soc board right now. --- Quote Start --- Hello Christoph, SDRAM is a complex chip that requires special logic to operate. It needs an external refresh mechanism to keep it going, I think this aspect is not in your code. Best Regards, Johi. --- Quote End --- what he's saying, you need a memory controller, thus can be integrated by using IP Cores, otherwise the Memorycontent wont be safed, because s"D"ram is dynamic, which means, bits are stored to capacitators which must be refreshed. (by a controller.) I consider right now using the onboard DDR3RAM, because its faster, but cant get any IP wordking till now on Quartus 17.1 ...