SDRAM in DE1

Make sure you are using the same PLL output both for the controller core and the DRAM chip. The DRAM chip must use the dedicated PLL pin output, and both clocks must be properly phase shifted. It is sometimes needed even when using slow clocks.

That is assuming it is a timing issue.

The chips are not identical, but almost. If you still want the original Powerchip datasheet, I think it is available. But again, they are all standard PC SDRAM compliant chips, whatever difference shouldn't be relevant.

Yes, I use one PLL with two outputs. System rise clock is behind sdram clock on 3ns. I played with various phase shift and clock frequency. The behavior was the same.

I think I found the issue. It is parameter named “Wrap sequence (Sequential/Interleave)” mentioned on datasheet. But I’m not sure. It seems to me that there is no way to control this parameter from standard SDRAM controller.

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I think I found the issue. It is parameter named “Wrap sequence (Sequential/Interleave)” mentioned on datasheet. But I’m not sure. It seems to me that there is no way to control this parameter from standard SDRAM controller.

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I doubt very much this is your problem. But if you want, you can change those parameters.

Look on your project folder, SOPC would produce a clear HDL source file with the SDRAM controller. You can edit it and change what you want. It will be overwritten anytime you regenerate the SOPC system though, but for the purpose of testing you probably don't mind.

Again, it is unlikely this is the problem. Build the memory test program available as a template, it is very good for the purpose of testing RAM timing issues. For better testing you need to add a DMA controller.

Did you put the PLL outside of the SOPC builder? If you did, please check the editable clock frequency field in the SOPC. Make sure it matches the value in the PLL settings. It seems like the UART input frequency was wrong, so the baud rate has been generated with incorrect referrence.

Wish this may help you.

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Hello All,

I have a small problem with sdram on my DE1. I use quartus 7.2sp2, NIOS and SDRAM controller from SOPC builder. I’ve cloned the basic design and SDRAM setting from Terasic’s DE1_NIOS project.

My program placed in sdram works well. I may successfully access data in sdram using word alignment. However the text from printf() function looks like crap and disordered.

Where is a problem here? I suppose I need the proper sdram timings. Could someone share the proper sdram settings?

Thank you.

Alexander.

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The primary reason for this is the use of printf() itself. printf() sends an interrupt to the processor (because printf works with jtag_uart) and you stand to loose several cycles of data. In fact printf() is not a recommended practice and should be avoided. If you write your data into some file and read it later, that should be still ok.

It is possible that it is also a printf issue, but in general it is timing issue.

Because when I program DMA to retrieve data from sdram then readed data was crap.

However, DMA write to sdram is ok.

(I used DMA in word transfer mode.)

Alexander.

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It is possible that it is also a printf issue, but in general it is timing issue.

Because when I program DMA to retrieve data from sdram then readed data was crap.

However, DMA write to sdram is ok.

(I used DMA in word transfer mode.)

Alexander.

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In that case, printf() is one of the two contributors to this error. printf() should not be used for printing data from the memories etc. You can use file read/write for this purpose. "Altera Host-Based File System" is a good utility for this purpose.

That said, the cause of your current error appears to stem up from incorrect specification of Read/Write cycles of the memory. I conclude this as you wrote DMA write to SDRAM is fine (though I would like to know how did you ascertain this). Try varying the cycles and reading the memory then.

I forgot to say that I was trying to get it working at slow clock frequency 30 MHz. Well, at now I have it working.

This is my recipe how to do this:

In the SOPC Builder set clock settings to 100MHz. It is very important to set this value despite the actual clock frequency.

It is possible to leave all timing setting by wizard default. Actually we have to decrease the value "Issue one refresh command every", but default value works fine for me.

Set sdram rise clock prior system clock on 3 ns.

That's all.

Alexander.