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I think I found the issue. It is parameter named “Wrap sequence (Sequential/Interleave)” mentioned on datasheet. But I’m not sure. It seems to me that there is no way to control this parameter from standard SDRAM controller.
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I doubt very much this is your problem. But if you want, you can change those parameters.
Look on your project folder, SOPC would produce a clear HDL source file with the SDRAM controller. You can edit it and change what you want. It will be overwritten anytime you regenerate the SOPC system though, but for the purpose of testing you probably don't mind.
Again, it is unlikely this is the problem. Build the memory test program available as a template, it is very good for the purpose of testing RAM timing issues. For better testing you need to add a DMA controller.
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