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Honored Contributor
Honored ContributorSDRAM in DE1
Hello All, I have a small problem with sdram on my DE1. I use quartus 7.2sp2, NIOS and SDRAM controller from SOPC builder. I’ve cloned the basic design and SDRAM setting from Terasic̵...
Altera_ForumHonored Contributor
Honored ContributorYes, I use one PLL with two outputs. System rise clock is behind sdram clock on 3ns. I played with various phase shift and clock frequency. The behavior was the same.
I think I found the issue. It is parameter named “Wrap sequence (Sequential/Interleave)” mentioned on datasheet. But I’m not sure. It seems to me that there is no way to control this parameter from standard SDRAM controller.
