sunyeong
New Contributor
1 year agoRequest of AXI bridge example for Arria 10 HPS to FPGA communication
Hi.
Our company is planning to develop new products using the Arria10 SoC.
So, I am checking the technologies needed for product development.
I need the feature for HPS to communicate with FPGA logic using an AXI bridge, but I'm having trouble finding related documentation on RocketBoard.
Looking at the TRM (Technical Reference Manual), it appears that it is accessed using Memory Map I/O.
It seems that each AXI bridge have 5 channels that consists of a number of signals. But memory offset of those signals arn't described.
I tried to find a sample application related to this function(HPS to FPGA Bridge) in GSRD, but it was not easy.
Could you please forward me any relevant examples or documents?
Regards,
Jung